A(1) Field of the invention
The invention is used in the field of digital signal processing and relates more particularly to a decimation, non-recursive linear phase FIR filter having a filter length N and a decimation factor q.
A decimation filter is a filter belonging to the category of filters arranged to change the sampling frequency associated with a digital signal and to adapt the frequency spectrum of the original digital signals to this changed sampling frequency. The original sampling frequency is reduced by the decimation factor q.
In such a filter precautions must be taken to prevent "aliasing" from occurring (see chapter D, reference 1).
The filter length N of the filter indicates the number of filter coefficients considered. This filter length determines the extent to which unwanted frequency components are suppressed and consequently the extent to which "aliasing" is prevented.
In a linear phase FIR filter the impulse response characterized by the N filter coefficients is symmetrical and finite.
A(2) Description of the prior art
As mentioned above a decimation filter is arranged to reduce the sampling frequency of a digital information signal by a factor of q, such that no aliasing occurs. Let it be assumed that this information signal is formed by a sequence of information signal samples x(n) which occur with the said sampling frequency, which will be denoted by 1/T. The quantity n in x(n) represents the number of the information signal sample, it holding that n=0, .+-.1, .+-.2, . . . Different embodiments of a decimation filter are known.
A first embodiment is described in reference 2 and comprises a digital filter whose output is connected to a switching device. The digital information signal is applied to the digital filter and this filter produces a digital auxiliary signal formed by a sequence of signal samples z(n), which also occur with the sampling frequency 1/T. These signal samples z(n) are applied to the switching device, which only passes those signal samples z(n) for which it holds that: n=iq, wherein i=0, .+-.1, .+-.2, . . . Thus, a digital output signal consisting of a sequence of output signal samples y(i), which occur with the desired sampling frequency 1/(qT) and for which it holds that y(i)=z(iq), appears at the output of the switching device.
This first embodiment of the decimating filter has the drawback that the signal samples z(n) which are not passed by the switching device are yet computed, which causes the internal processing speed to be really unnecessarily high.
Reference 3 proposes a second embodiment. In this second embodiment a considerably lower internal processing speed is required than in the first embodiment. This second embodiment comprises a digital filter whose input is connected to the output of an input buffer wherein, depending on the construction of the digital filter, q or q-1 consecutive information signal samples x(n) are stored. These signal samples x(n) stored in this input buffer are transferred to the digital filter in a time interval which is at the utmost equal to one sampling period T. This digital filter now has a time interval of a length q(-1)T at its disposal to compute one output signal sample y(i). This second embodiment has the drawback that it requires a high clock frequency to transfer the signal samples stored in the input buffer to the digital filter.
The digital filters used in the above-described embodiment are preferably implemented as non-recursive digital FIR filters. These FIR filters now determine predominantly the complexity of the decimation filter. Two structures are of main importance for non-recursive digital filters.
A first FIR filter is shown in, for example FIG. 9.1 of reference 4 and is sometimes denoted as a tapped delay line filter. This FIR filter comprises a digital delay line in the form of a cascade arrangement of a plurality of shift register sections, each of these sections being arranged for storing one signal sample x(n) and having, consequently, a delay time T. Each one of the outputs of these shift register sections are connected to the input of an adder device via a multiplier. A filter coefficient is applied to each of these multipliers.
A second FIR filter structure is shown in, for example, FIG. 9.2 of reference 4. This FIR filter comprises a circulating delay line which is a circulating shift register comprising a cascade arrangement of N shift registers, each having been arranged for storing one signal sample x(n). These signal samples are applied consecutively and together with an associated filter coefficient to a multiplier device producing product signal samples which are applied to an accumulator.
Relative to the first FIR filter structure, the second FIR filter structure has the advantage that it requires only one multiplier device. The drawback is, however, that in this second structure the frequency with which the signal samples stored in the shift register must be shifted is now N-times higher than the frequency 1/T with which these signal samples are applied to this shift register.
If a linear phase FIR filter must be realized, it is possible to reduce the typical drawback of the first FIR filter structure as well as the typical drawback of the second FIR filter structure. In these circumstances it is possible to choose the value of N such that the filter coefficients are equal pair-wise. The signal samples which must now be multiplied by equal filter coefficients can now first be added together, so that approximately N/2 multiplications need not be performed.
The first FIR filter structure can now be simplified to the structure shown in FIG. 10 of reference 5 and in which approximately N/2 of the originally present multipliers have been replaced by adders, which makes the whole structure less complex.
The second FIR filter structure can now be modified to form one of the structures shown in the FIGS. 3 to 11 inclusive of reference 6. In the structures shown there it is achieved that the frequency with which the signal samples are shifted in the shift register is lower than in the original structure. The complexity of the linear phase FIR filter structures obtained in this manner is, however, generally greater than the complexity of the non-linear phase FIR filter structures comprising a circulating delay line.